`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/02/17 15:55:13
// Design Name: 
// Module Name: mutiple
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mutiple(
input [3:0]a,
input [3:0]b,
output reg [7:0]p
    );
    reg [7:0] pv;
    reg [7:0] ap;
    integer i;

    always@(*)
    begin 
        pv = 8'b00000000;
        ap = {4'b0000,a};
        for(i = 0;i <= 3;i = i+1)
        begin
        
            if(b[i] == 1)
            begin
            pv = pv + ap;
            ap = {ap[6:0],1'b0};
            end
            else
            ap = {ap[6:0],1'b0};
        end
        p = pv;
    end

endmodule
